/* Shared presentation refinements for Dolphin PCIe reference-architecture pages. */
body.pcie-architecture-page .arch-section {
  padding: clamp(54px, 6vw, 84px) 0;
}

body.pcie-architecture-page .arch-section-head {
  max-width: 900px;
  margin-bottom: 30px;
}

body.pcie-architecture-page .arch-section-head p {
  max-width: 760px;
}

body.pcie-architecture-page .arch-process__item,
body.pcie-architecture-page .arch-definition__item,
body.pcie-architecture-page .arch-block,
body.pcie-architecture-page .arch-fit {
  box-shadow: 0 12px 30px rgba(16, 40, 62, .055);
}

body.pcie-architecture-page .arch-process__item {
  min-height: 0;
  padding: 24px;
}

body.pcie-architecture-page .arch-process__item::before {
  margin-bottom: 24px;
}

body.pcie-architecture-page .arch-topology-panel {
  padding: clamp(20px, 2.6vw, 34px);
  box-shadow: 0 18px 42px rgba(16, 40, 62, .07);
}

body.pcie-architecture-page .arch-definition__item,
body.pcie-architecture-page .arch-block,
body.pcie-architecture-page .arch-fit {
  padding: 22px;
}

body.pcie-architecture-page .arch-block,
body.pcie-architecture-page .arch-fit {
  min-height: 170px;
}

body.pcie-architecture-page .arch-block small,
body.pcie-architecture-page .arch-fit small {
  margin-bottom: 14px;
}

body.pcie-architecture-page .arch-matrix {
  box-shadow: 0 16px 38px rgba(16, 40, 62, .055);
}

body.pcie-architecture-page .arch-matrix__row:nth-child(even) .arch-matrix__value {
  background: #fbfdfe;
}

body.pcie-architecture-page .arch-matrix__key {
  border-right: 1px solid #e3ebf0;
}

body.pcie-architecture-page .arch-section--dark {
  color: #f7fbfd !important;
  background: linear-gradient(135deg, #091f31 0%, #0d2d43 100%);
}

body.pcie-architecture-page .arch-section--dark .arch-eyebrow {
  color: #8eddf2 !important;
}

body.pcie-architecture-page .arch-section--dark h2,
body.pcie-architecture-page .arch-section--dark h3,
body.pcie-architecture-page .arch-section--dark strong {
  color: #f7fbfd !important;
}

body.pcie-architecture-page .arch-section--dark p,
body.pcie-architecture-page .arch-section--dark .arch-section-head p,
body.pcie-architecture-page .arch-section--dark .arch-input span {
  color: rgba(238, 246, 250, .84) !important;
}

body.pcie-architecture-page .arch-section--dark .arch-input {
  background: rgba(5, 24, 38, .72);
}

body.pcie-architecture-page .arch-canvas__head span,
body.pcie-architecture-page .arch-canvas__foot span,
body.pcie-architecture-page .arch-node small {
  color: #a6e2f1 !important;
}

body.pcie-architecture-page .arch-node strong {
  color: #f8fcfe !important;
}

body.pcie-architecture-page .arch-node em {
  color: rgba(239, 247, 251, .82) !important;
}

body.pcie-architecture-page .arch-final-cta h2 {
  color: #f8fcfe !important;
}

body.pcie-architecture-page .arch-final-cta p {
  color: rgba(239, 247, 251, .84) !important;
}

body.pcie-architecture-page .dolphin-reference-panel {
  box-shadow: 0 18px 44px rgba(16, 40, 62, .07);
}

@media (max-width: 760px) {
  body.pcie-architecture-page .arch-section {
    padding: 48px 0;
  }

  body.pcie-architecture-page .arch-section-head {
    margin-bottom: 24px;
  }

  body.pcie-architecture-page .arch-block,
  body.pcie-architecture-page .arch-fit {
    min-height: 0;
  }

  body.pcie-architecture-page .arch-matrix__key {
    border-right: 0;
  }
}